Project Objective
This project aims to model an HVDC-integrated bus system and analyse transient performance during AC-side or DC-side faults using DIgSILENT PowerFactory 2024. It is suitable for engineering scholars and PhD researchers who need a clear model explanation, simulation workflow and thesis-ready result discussion.
System Architecture
The implementation can be organized as a modular research model with plant, controller, measurement and result-visualization blocks. This page is structured for literature extension, methodology writing and reproducible simulation reporting.
- AC bus network connected through HVDC converter terminals
- converter control modes for sending and receiving-end operation
- AC line, DC link and converter measurement channels
- fault events for bus, line or DC-side transient studies
Research Methodology
The recommended methodology begins with base-case modelling, parameter selection and initial validation. The next step is to introduce the control, energy-management, protection or fault-diagnosis algorithm and evaluate the system under carefully selected operating conditions. The final report should compare baseline and improved responses using measurable indicators.
Recommended Simulation Cases
- pre-fault steady-state load-flow validation
- three-phase AC bus fault and voltage recovery
- DC-side pole or line disturbance response
- fault-clearing time sensitivity and transient performance comparison